The present invention relates to semiconductor power switching devices, and more particularly, to a method and device for improving manufacturing yield and performance of thyristor-based devices having plural high yield sub-elements that are separated through the novel use of built-in diode regions.
The types of semiconductor power switching devices in which the present invention will find application are thyristor-based devices that have four layers of alternating semiconductor types in which the conduction current crosses three junctions; that is, they include 3 P-N junctions, such as junctions J1-3 illustrated in FIG. 1. Such devices may comprise a single silicon chip and may include a large number of closely packed cells 10 in a surface thereof. Thyristor-based devices are well-known in the art and include, among others, MOS controlled thyristors (MCTs), and gate turnoff thyristors (GTOs). The switching action of MOS controlled devices is accomplished by the application of voltage signals to a gate 12 overlying the cellular structure. For example, the MCT illustrated in FIG. 1 is turned on by an ON-FET when the channel 14 of the ON-FET is activated by the electric field caused by a small voltage of a first polarity (e.g., minus 5 volts) in the gate. The voltage starts a regenerative action that turns on an upper transistor (PNP transistor including J3 and J2) and a lower transistor (NPN transistor including J1 and J2) in the device so that the MCT conducts a current between its anode and cathode (i.e., the device is turned on). The MCT is turned off when a small voltage of the opposite polarity (e.g., plus 7 volts) is supplied to the gate, activating a channel 16 in the OFF-FET. When the MCT is being turned off, the gate voltage creates an electric field in the channel 16 causing the semiconductor type of the region beneath the gate to convert to the opposite semiconductor type, effectively eliminating the emitter-base junction J3 at the channel 16. The channel 16 becomes a conductive path around the emitter that turns off the upper transistor and stops MCT conduction (the device is in a blocking condition).
The current handling capability of a semiconductor power switching device is typically determined by, among other factors, its root mean square (RMS) current rating and the size of the active area carrying the current. For example, a device with an RMS current rating of 150 Amps/cm.sup.2 and an active area of 2 cm.sup.2 would have a current handling capability of 300 Amps. In other words, for a given RMS current rating, the current handling capability of a device may be increased simply by increasing the amount of active area. The active area of the device is that portion which is controlled by the gate.
High voltage semiconductor devices may also include a termination region about the perimeter of the active area of the device. The termination region provides a transition from the high electric field in the active area to the lower field tolerated by the material surrounding the device. The objective of the termination region is to spread the voltage gradient between the active area and the edge of the device over the termination region without introducing excess leakage and without trapping surface charges that could cause localized avalanching or could induce channel leakage in the underlying silicon. The size of the termination region may vary depending on, among other factors, the voltage rating of the device, but for a given device size, any area devoted to the termination region reduces the amount of active area available in the device. Consequently, it is desirable in the design of semiconductor power devices to decrease the amount of termination region in the device relative to the amount of active area so that the current carrying capability of the device may be optimized for a particular device size. For example, a method of providing a near optimum amount of active area is to provide one large active area surrounded by a single peripheral termination region.
However, the likelihood that the device will have a fatal defect also increases with increasing size of the active area. The device yield (the percent of devices produced that are operable) for fine lithography MOS gated devices, such as the MCT illustrated in FIG. 1, is driven primarily by gate yield. The gate 12 of such devices is a sheet of polysilicon isolated from an overlying power electrode by a thin insulating layer. The manufacture of thin insulating layer is subject to defects, such as pinholes, particles, photo errors, etc., which may electrically short the gate to the power electrode rendering the device inoperable. The larger the active area (i.e., the larger the gate), the lower the device yield. For example, device yield for a particular manufacturing line for a particular device having an active area of 0.25 cm.sup.2 may be 75 percent (three-quarters of the devices fabricated will likely be operable), while the same line producing the same device with an active area of 5 cm.sup.2 may have a yield of less than 10 percent. As is apparent, the manufacturing process for a device with a large active area may be quite wasteful, for example, providing only one operable device out of ten devices produced.
Another method of manufacturing devices with large active areas is to produce a number of small devices, each having its own termination region and a small active area with resultant higher device yield, and to assemble the numerous small devices in a module to produce the total active area required. This approach may be attractive where the voltage rating of the assembled device is relatively low and the size of the termination region for each small active area device can be correspondingly small. However, as the device voltage rating increases, the width required for the termination region also increases. For example, an MCT device of less than about 1,000 volts may have a termination region that covers about 20 percent of the device surface, while an MCT device with a voltage rating of 2,500 volts may need a termination region that covers more than 40 percent of the device surface.
In the device and method of the present invention, the total active area of a monolithic semiconductor power switching device is surrounded by a single peripheral termination region, and the total active area is divided into sub-elements, each of which is an active area with its own gate, and power electrode contacts. The likelihood that an active area will be operable increases with decreasing active area size, and an active area size may be selected that provides acceptable device yield and capability and manufacturing complexity. However, even then it is likely that not all of the active areas in a particular device will be operable (i.e., one of the sub-elements may have a bad gate). Thus, one or more of the operable active areas will probably be adjacent an inoperable active area. By way of example, and with reference to FIG. 2 in which six active areas 24, 26 are placed inside a termination region 22, one active area 24 may be inoperable due to a defect. The effect of an inoperable active area on device capability may be taken into account by statistically determining how many active areas are needed to achieve a desired device capability, given that a statistically determinable number of active areas will be inoperable. As an operable device may have inoperable active areas that are, in effect, open circuits, it is desirable to avoid direct connections to the inoperable active areas. Accordingly, once the inoperable active areas have been identified during the manufacturing process, the inoperable active areas are not connected to the gate or the anode for the device, such as illustrated in FIG. 2 by the omission of connecting lines to active area 24.
Further, and as will be discussed in more detail below, it has been found that when an operable active area 26 is turned on, carriers (i.e., holes and electrons) from the operable active area 26 may flow into an inoperable (and unconnected) adjacent active area 24. When the holes and electrons flow into the inoperable active area, they may start the regenerative action of the thyristor therein. Because there is no gate attached to the inoperable active area 24, the regenerative action cannot be stopped and the device cannot be turned off. The carriers in the inoperable area 24 may reach the adjacent operable area 26 starting an unwanted regenerative thyristor action there as well, causing the device to become inoperable.
Accordingly, it is an object of the present invention to provide a novel method and device for separating active areas in a monolithic semiconductor power switching device that obviates the problems of the prior art.
It is a further object of the present invention to provide a novel method and device for separating active areas in a monolithic semiconductor power switching device so that current from an operable one of the active areas does not turn on an inoperable one of the active areas.
It is still a further object of the present invention to provide a novel method and device in which plural active areas in a thyristor-based semiconductor device are separated by diode regions internal to the device that inhibit flow between active areas.